Compiler optimizations in the PACT HDL behavioral synthesis tool for ASICs and FPGAs

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 189-192

  Tang, Xiaoyong ^a   Jiang, Tianyi ^a   Jones, A ^a   Banerjee, P ^a  

^a Northwestern University   (United States)

Author keywords

Algorithm design and analysis; Application specific integrated circuits; Field programmable gate arrays; Flow graphs; Hardware design languages; High level languages; High level synthesis; Optimizing compilers; Program processors; System on a chip

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER PROGRAMMING LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOW GRAPHS; HARDWARE; HIGH LEVEL LANGUAGES; HIGH LEVEL SYNTHESIS; LOGIC SYNTHESIS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; SYNTHESIS (CHEMICAL); SYSTEM-ON-CHIP;

ALGORITHM DESIGN AND ANALYSIS; BEHAVIORAL SYNTHESIS; COMPILER OPTIMIZATIONS; FPGAS AND ASICS; HARDWARE DESIGN; HARDWARE DESIGN LANGUAGE; OPTIMIZING COMPILERS; SYSTEM ON A CHIP;

PROGRAM COMPILERS;

EID: 84945351611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241490     Document Type: Conference Paper

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