An 800-μW H.264 baseline-profile motion estimation processor core

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 99-102

  Iinuma, Takahiro ^a   Miyakoshi, Junichi ^a   Murachi, Yuichiro ^a   Matsuno, Tetsuro ^a   Hamamoto, Masaki ^a   Ishihara, Tomokazu ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a   Miyama, Masayuki ^b  

^a KOBE UNIVERSITY   (Japan)

^b KANAZAWA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOTION ESTIMATION; PIXELS; TRANSISTORS; VLSI CIRCUITS;

PORTABLE VIDEO; PROCESSING FLOW; SYSTOLIC ARRAY DATAPATH ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 34250887581     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357861     Document Type: Conference Paper

References (6)

1. ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC,"Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, " 2003.
2. ISO/IEC | ITU-T VCEG, "Fast Integer Pel and Fractional Pel Motion Estimation for JVT, "JVT-F017, 2002
3. JM 8.5, http://iphome.hhi.de/suehring/tml/.
4. Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Junichi Miyakoshi, Masayuki MIYAMA, and Masahiko YOSHIMOTO,"A 95 mW MPEG2 MP@HL Motion Estimation Processor Core or Portable High-Resolution Video Application", IEICE Trans. Fundamentals, VOL.E88-A, NO. 12, pp.3492-3499, December 2005.
5. Juniehi MIYAKOSHI, Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Masayuki MIYAMA, and Masahiko YOSHIMOTO, "A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation", IEICE Trans. Electoronics, VOL.E88-C, NO.4, pp.559-569, April 2005
6. Y-W. Huang, T-C. Chen, C-H.Tsai, C-Y.Chen, T-W. Chen, C-S. Chen, C-F. Shen, S-Y. Ma, T-C. Wang, B-Y. Hsieh, H-C. Fang, L-G. Chen, "A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications", IEEE International Solid-state Circuit Conference, pp128-129, January 2005