A study of pipeline architectures for high-speed synchronous DRAM's

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 10, 1997, Pages 1597-1603

  Yoo, Hoi Jun ^a  

^a Kangwon National University   (South Korea)

Author keywords

DRAM chips; Pipelines

Indexed keywords

PIPELINE ARCHITECTURES; PROGRAM EXECUTION TIME;

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; NUMERICAL METHODS;

RANDOM ACCESS STORAGE;

EID: 0031257062     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634671     Document Type: Article

References (15)

1. Y. Takai, M. Nagase, M. Kitamura, Y. Koshikawa, N. Yoshida, Y. Kobayashi, T. Obara, Y. Fukuzo, and H. Watanabe, "250 Mbyte/sec synchronous DRAM using a 3-stage pipelined architecture," in Symp. VLSI Circuit Dig. Tech. Papers, June 1993, pp. 59-60.
2. Y. Choi, M. Kim, T. Kim, S. Lee, H. Lee, C. Park, S. Lee, C. Kim, B. Lee, S. Cho, E. Haq, J. Karp, and D. Chin, "16 Mbit synchronous DRAM with 125 Mbyte/sec data rate," in Symp. VLSI Circuit Dig. Tech. Papers, June 1993, pp. 65-66.
3. A. Fujiwara, H. Kikukawa, K. Matsuyama, M. Agata, S. Iwanari, M. Fukumoto, T. Yamada, S. Okada, and T. Fujita, "A 200 MHz 16 Mbit synchronous DRAM with block access mode," in Symp. VLSI Circuit Dig. Tech. Papers, June 1994, pp. 79-80.
4. Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, and T. Ema, "A 150 MHz 4 bank 64 Mbit SDRAM with address incrementing pipeline scheme," in Symp. VLSI Circuit Dig. Tech. Papers, June 1994, pp. 81-82.
5. Y. Sakai, K. Oishi, M. Matsumoto, S. Wada, T. Sakashita, and M. Katayama, "A synchronous DRAM with new high-speed I/O lines method for multimedia age," in IEICE Trans. Electron., vol. E78C, no. 7, pp. 782-788, July 1995.
6. H. J. Yoo, K. W. Park, C. H. Chung, S. J. Lee, H. J. Oh, K. W. Kwon, J. S. Son, W. S. Min, and K. H. Oh, "A 150 MHz 8-banks 256 M synchronous DRAM .with the wave pipelining method," in ISSCC, Dig. Tech. Papers, Feb. 1995, pp. 250-251.
7. S. J. Lee, K. W. Park, C. H. Chung, J. S. Son, K. H. Park, S. H. Shin, S. T. Kim, J. D. Han, H. J. Yoo, W. S. Min, and K. H. Oh, "A low noise 32 bit-wide 256 M synchronous DRAM with column decoded I/O line," in Symp. VLSI Circuit Dig. Tech. Papers, June 1995, pp. 113-114.
8. J. M. Han, J. B Lee, S. S. Yoon, S. J. Jeong, C. Park, I. J. Cho, S. H. Lee, and D. I. Seo, "Skew minimization techniques for 256 Mbit synchronous DRAM and beyond," in Symp. VLSI Circuit Dig. Tech. Papers, June 1996, pp. 192-193.
9. S. A. Przybylski, Cache and Memory Hierarchy Design. San Francisco, CA: Morgan Kaufman, 1990.
10. Intel Corporation, Pentium Processor Family Developer's Manual, 1996.
11. J. L. Hennesy and D. A. Patterson, Computer Architecture, A Quantitative Approach. San Francisco, CA: Morgan Kaufman, 1996.
12. M. R. Zargham, Computer Architecture, Single and Parallel Systems. Upper Saddle River, NJ: Prentice Hall, 1996.
13. D. C. Wong, G. D. Micheli, M. J. Flynn, and R. E. Huston, "A bipolar population counter using wave pipelining to achieve 2.5 × normal clock frequency," in ISSCC, Dig. Tech. Papers, Feb. 1992, pp. 56-57.
14. T. Williams, "Self-timed clocked logic techniques," presented at Proc. Symp. VLSI Circuit Workshop, June 1996.
15. C. T. Gray, W. Liu, and R. K. Cavin III, Wave Pipelining: Theory and CMOS Implementation. Norwell, MA: Kluwer, 1994.