A 6-bit low-power compact flash ADC using current-mode threshold logic gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3938-3941

  Akiyama, Shunsuke ^a   Waho, Takao ^a  

^a SOPHIA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FLASH MEMORY; GATES (TRANSISTOR); THRESHOLD LOGIC;

LOW POWER COMPACT FLASH ADC; SAMPLING FREQUENCY; THRESHOLD LOGIC GATES;

ANALOG TO DIGITAL CONVERSION;

EID: 34250788961     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. David A. Johns and Ken Martin, "Analog Integrated Circuit Design," John Wiley and Sons, Inc., 1997 (ISBN 0-471-14448-7).
2. Yuuki Tsuji and Takao Waho, "Design of Flash Analog-to-Digital Converters using Resonant-Tunneling Circuits," IEICE Trans. Electronics, Vol. E87-C, no. 11, pp. 1863 - 1868, November 2004.
3. M. Padure, S. Cotofana, C. Dan, M. Bodea, and S. Vassiliadis. "A New Latch-Based Threshold Logic Family," Proceedings of International Semiconductor Conference (CAS), vol. 2, pp. 531 - 534, October 2001.
4. Mohamed W. Aliam and Mohamed I. Elmasry, "Dynamic Current Mode Logic (DyCML): A New Low-Power High-Performance Logic Style," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 550-558, March 2001.
5. K. Uyttenhove, A. Marques, and M. Steyaert, "A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction," Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 249-252, May 2000.
6. Michael Choi and Asad A. Abidi, "A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, December 2001.
7. Sunghyun Park, Sangwon Yoon and Senol Mutlu, "A 6-b 800-MSample/s A/D Converter in 0.35-μm CMOS," http://www.eecs.umich.edu/~mpflynn/ teaching/design_ontest/fall_2002:/reports/10_Multu.pdf.