Very fast carry energy efficient computation based on mixed dynamic/transmission-gate full adders

Electronics Letters

Volumn 43, Issue 13, 2007, Pages 707-709

  Alioto, M ^a   Palumbo, G ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; PRODUCT DESIGN;

CARRY CHAINS; CMOS TECHNOLOGY; FAST DOMINO LOGIC;

ADDERS;

EID: 34250747443     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20070752     Document Type: Article

References (7)

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3. Alioto, M., and Palumbo, G.: ' Analysis and comparison on full adder block in sub-micron technology ', IEEE Trans. Very Large Scale Integr. (VLSI) Systems, 2002, 10, (6), p. 806-823 1063-8210
4. Chang, C.-H., Gu, J., and Zhang, M.: ' A review of 0.18m full adder performances for tree structured arithmetic circuits ', IEEE Trans. Very Large Scale Integr. (VLSI) Systems, 2005, 13, (6), p. 686-695 1063-8210
5. Krambeck, R.H., Lee, C.M., and Law, H.-F.S.: ' High-speed compact circuits with CMOS ', IEEE J. Solid-State Circuits, 1982, 17, (3), p. 614-619 10.1109/JSSC.1982.1051786 0018-9200
6. Harris, D.: Skew-tolerant circuit design, (Morgan Kaufmann Publishers, 2001)
7. Gonzalez, R., Gordon, B.M., and Horowitz, M.: ' Supply and threshold voltage scaling for low power CMOS ', IEEE J. Solid-State Circuits, 1997, 32, (8), p. 1210-1216 10.1109/4.604077 0018-9200