Advanced substrate engineering for the nanotechnology era

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2006, Pages 78-79

  Mazure, Carlos ^a  

^a PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

OPTIMIZATION; PRODUCT DESIGN; SUBSTRATES; VLSI CIRCUITS;

ADVANCED SUBSTRATE ENGINEERING; DEVICE PERFORMANCE;

NANOTECHNOLOGY;

EID: 34250319776     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2006.251074     Document Type: Conference Paper

References (17)

1. G.K. Celler and S. Cristoloveanu, J. Appl. Phys., vol. 93, p.4955 (2003).
2. D. Greenlaw et al.; IEDM Tech. Dig., pp. 277-280 (2003).
3. http://public.itrs.net/
4. C. Maleville & C. Mazure, Solid State Elect., vol. 48-6, p. 855 (2004).
5. C. Raynaud et al.; Silicon-On-Insulator Technology and Devices XII, ECS Proc., vol 2005-03, pp. 331-344 (2005).
6. A. Viviani, et al.; IEDM Tech. Digest, pp. 713-716 (1995).
7. T. Matsumoto et al.; IEDM Tech. Digest, pp.219-222 (2001).
8. P. Fazan, IEEE Int. SOI Conf., p. 10 (2002).
9. T. Oshawa et al., Proc. ISSCC, p. 152 (2002).
10. T. Shino et al., Proc. Symp. VLSI Circuits, (2004).
11. S. Okhonin et al.; IEEE EDL, 23, p. 85 (2002).
12. C. Mazure & I. Cayrefourcq; IEEE Int. SOI Conf., p.1 (2005).
13. K. Rim et al.; IEDM Tech. Dig., p. 49 (2003).
14. A. Thean et al.; Proc. Symp. VLSI Tech, p. 134 (2005).
15. N. Bresson et al.; IEEE Int. SOI Conf., p. 62 (2004).
16. O. Rayssac et al.; Silicon-On-Insulator Technology and Devices X, ECS Proc., vol 2001-03, p. 39 (2001).
17. R. Tsuchiya et al.; IEDM Tech Dig., pp. 631-634 (2004).