Fixed-current method for programming large floating-gate arrays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3934-3937

  Chakrabartty, Shantanu ^a   Cauwenberghs, Gert ^b  

^a MICHIGAN STATE UNIVERSITY   (United States)

^b Johns Hopkins University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE MEASUREMENT; CMOS PROCESS; CONVENTIONAL APPROACH; CURRENT MEASUREMENTS; FLOATING GATE TRANSISTORS; FLOATING GATES; FLOATING-GATE; FLOATING-GATE PROGRAMMING; MEASURED RESULTS; PICOAMPERES; POSITIVE FEEDBACK; VARIABLE CONTROL;

BANDPASS FILTERS; ELECTRIC CURRENT MEASUREMENT; PULSE GENERATORS; SIGNAL GENERATORS;

FEEDBACK;

EID: 34247477149     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465491     Document Type: Conference Paper

References (6)

1. P. Hasler,B. Minch,J. Dugger and C. Diorio, Adaptive Circuits and synapses using PFET Floating Gate Devices, Learning on Silicon: Kluwer Academic Publishers, Boston 1999.
2. C. Dorio,P. Hasler,B. Minch and C.A. Mead, "A Single-Transistor Silicon Synapse," IEEE Trans. Electron Devices, vol. 43 (11), Nov. 1996.
3. Amin,A.A.M, "Design, selection and implementation of flash erase EEPROM memory cells," IEE Proceedings Circuits, Devices and Systems vol. 139 (3), Jun. 1992.
4. Cunha,A.I.A, Schneider, M.C, and Galup-Montoro,C., "A MOS transistor model for analog circuit design," IEEE Journal of Solid State Circuits, vol. 33 (10), pp. 1510-1519, Oct. 1998.
5. Enz, C.C, Krummenacher, F., and Vittoz, E.A, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applicaitons," Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, 1995.
6. Chakrabartty, S. and Cauwenberghs, G. "Sub-microwatt Analog VLSI Support Vector Machine for Pattern Classification and Sequence Estimation" to appear Adv in Neural Information Processing Systems Cambrige: MIT Press, 2005.