Low gate charge 20V class trench-aligning lateral power MOSFET

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn 2006, Issue , 2006, Pages

  Matsunaga, S ^a   Sawada, M ^a   Sugi, A ^a   Takagiwa, K ^a   Fujishima, N ^a  

^a FUJI ELECTRIC CO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; ELECTROSTATIC DISCHARGE; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR JUNCTIONS;

HUMAN BODY MODEL (HBM); LIGHTLY DOPED DRAIN (LDD); LOW GATE CHARGE; TRENCH LATERAL POWER MOSFET (TLPM);

ELECTRIC CHARGE;

EID: 34247473526     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. H. Deng et al, "Design of a monolithic 2 MHz fast transient voltage regulator chip", ISPSD, pp.383-386, 2004.
2. A. Q, Huang et al, "Low voltage power devices for future VRM", ISPSD, pp.395-398, 1998.
3. C. Grelu et al, "Switching loss optimization of 20V devices integrated in a 0.13um CMOS technology for portable applications", Proceedings of ISPSD, pp.339-342, 2005.