Switching loss optimization of 20V devices integrated in a 0.13 μm CMOS technology for portable applications

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn , Issue , 2005, Pages 339-342

  Grelu, C ^a,b   Baboux, N ^b   Bianchi, R A ^a   Plossu, C ^b  

^a STMICROELECTRONICS   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC LOSSES; PORTABLE EQUIPMENT; SWITCHING;

DIFFUSED-MOSFET; DRAIN OVERLAP; DRIFT-MOSFET; GATE CAPACITANCE;

MOSFET DEVICES;

EID: 27744440749     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

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2. S. Livand "Small signal MOSFET models for analog circuit design" IEEE Journal of Solid State Circuits, vol. 1, no6, SC-17, 1982.
3. N. Baboux and al, "A new stucture to monitor electrical transients during programming of EEPROM memory cells" Microelectronics Reliability, vol 44 p 1745-1750, 2004.
4. S.T.Peake "A novel high side FET with reduced switching loss" ISPSD, p 362-365, 2003.