Efficient multibit quantization in continuous-time ΣΔ modulators

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 4, 2007, Pages 757-767

  De Maeyer, Jeroen ^a,b   Rombouts, Pieter ^a   Weyten, Ludo ^a  

^a GHENT UNIVERSITY   (Belgium)

^b ON SEMICONDUCTOR   (United States)

Author keywords

Analog to digital conversion; Quanitzation; Sigma delta ( modulation

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; COMPUTER SIMULATION; FEEDBACK; JITTER;

MULTIBIT FEEDBACK LOOP; MULTIBIT QUANTIZATION;

DELTA SIGMA MODULATION;

EID: 34247252890     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.890607     Document Type: Article

References (16)

1. R. Schreier, "An emperical study of higher order single-bit delta - sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 40, no. 8, pp. 461-466, Aug. 1993.
2. E. J. van der Zwan and E. C. Dijkmans, "A 0.2-mW CMOS ∑Δ modulator for speech coding with 80-dB dynamic range," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1873-1880, Dec. 1996.
3. J. A. Cherry and W. M. Snelgrove, "Clock jitter and quantizer metastability in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 661-676, Jun. 1999.
4. Z. Zhang and G. Temes, "Multibit oversampled ∑Δ A/D converter with nonuniform quantization," Electron. Lett., vol. 27, no. 6, pp. 528-529, Mar. 1991.
5. R. Schreier and B. Zhang, "Delta-Sigma modulators employing continuous-time circuitry," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43, no. 4, pp. 324-332, Apr. 1996.
6. J. De Maeyer, J. Raman, P. Rombouts, and L. Weyten, "Controlled behavior of the STE in CT ∑Δ modulators," Electron. Lett., vol. 41, no. 16, pp. 896-897, Aug. 2005.
7. J. De Maeyer, J. Raman, P. Rombouts, and L. Weyten, "STF behaviour in a CT ∑Δ modulator," in Proc. IEEE Int. Conf. on Electr. Circuits Syst. (ICECS), Gammarth, Tunesié, Dec. 2005, vol. 12, op CD.
8. J. G. Kenney and L. R. Carley, "Desing of multibit noise-shaping data converters," Anal. Integr. Circuits Signal Process., vol. 3, pp. 259-272, May 1993.
9. J. De Maeyer, P. Rombouts, and L. Weyten, "Nyquist criterion based design of continuous-time ∑Δ modulators," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS), Kos, Greece, May 21-24, 2007, pp. 2501-2504.
10. S. Patón, A. Di Giandomenico, L. Hernández, A. Wiesbauer, T. Pötscher, and M. Clara, "A 70-mW 300-MHz CMOS continuous-time ∑Δ ADC with 15-MHz bandwidth and 11 bits of resolution," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1056-1063, Jul. 2004.
11. J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, "Wideband low-distortion delta - sigma ADC topology," Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
12. H. van der Ploeg, "A 3.3-V 10-bit 25-MSample/s two-step ADC in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1803-1811, Dec. 1999.
13. H. Schuurmans, "Sigma Delta A/D converter with pseudo flash converter," WO Patent No. 03/100984, Dec. 4, 2003.
14. L. Dörrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, "A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005.
15. J. T. Tou, Digital and Sampled-Data Control Systems. New York: McGraw-Hill, 1959.
16. D. Lindoiff, Theory of Sampled-Data Control Systems. New York: Wiley, 1966.