The use of UML sequence diagram for system-on-chip system level transaction-based functional verification

Proceedings of the World Congress on Intelligent Control and Automation (WCICA)

Volumn 2, Issue , 2006, Pages 6173-6177

  Yu, JinShan ^a   Li, Tun ^a   Tan, QingPing ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

Functional verification; SoC; Transaction; UML sequence diagrams

Indexed keywords

FUNCTION EVALUATION; LOGIC DESIGN; MICROPROCESSOR CHIPS; VERIFICATION;

FUNCTIONAL VERIFICATION; SEQUENCE DIAGRAMS; SYSTEM LEVEL FUNCTIONAL SPECIFICATION;

UNIFIED MODELING LANGUAGE;

EID: 34047241444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WCICA.2006.1714269     Document Type: Conference Paper

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