A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2, Issue , 2006, Pages

  Yeh, Chingwei ^a   Wang, Chao Ching ^a   Lee, Lin Chi ^a   Wang, Jinn Shyan ^a  

^a Nat'l Chung Cheng University   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MEGA-SYMBOLS (MSYM); VARIABLE-LENGTH CODES (VLC);

BIT ERROR RATE; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS; MOTION PICTURES; MULTIMEDIA SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; TRANSISTORS;

IMAGE COMPRESSION;

EID: 34047134549     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A. Huffman, "A method for the construction of minimum-redundancy codes," Proc. IRE, vol. 40, pp. 1098-1101, Sept. 1952.
2. Mukherjee, N. Ranganathan, J. W. Flieder, and T. Acharya, "MARVLE: A VLSI chip for data compression using tree-based codes," IEEE Trans. VLSI Syst., vol. 1, pp. 203-213, June 1993.
3. Y. Ooi, A. Taniguchi, and S. Demura, "A 162 Mbits/s variable length decoding circuit using an adaptive tree search technique," in Proc. IEEE Custom Integrated Circuits Conf., 1994, pp. 107-110.
4. R. Hashemian, "Design and hardware implementation of a memory efficient Huffman decoding," IEEE Trans. Consumer Electron., vol. 40, pp. 345-352, Aug. 1994.
5. S.M. Lei and M.T. Sun, "An entropy coding system for digital HDTV applications," IEEE Trans. Circuits Syst. VideoTechnol., vol. 1, pp. 147-155, Mar. 1991.
6. S.F. Chang and D.G Messerschmitt, "Designing a high-throughput VLC decoder, Part I-Concurrent VLSI architectures," IEEE Trans. Circuits Syst. for Video Tech., vol. 2, pp. 187-196, June 1992; Also in: H.D. Lin and D.G Messerschmitt, "Designing a high-throughput VLC decoder Part II - Parallel decoding methods," IEEE Trans. Circuits Syst. Video Tech., vol. 2, pp. 197-206, June 1992.
7. B.W.Y. Wei and T.H. Meng, "A parallel decoder of programmable Hufiman codes," IEEE Trans. Circuits Syst. VideoTechn., vol. 5,pp.175-178, Apr. 1995.
8. S.H. Cho, et. al., "A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning," IEEE Trans. VLSI Syst., 7(2), pp.249-257, June 1999.
9. S.W. Lee and I.C. Park, "A Low-Power Variable Length Decoder for MPEG-2 Based on Successive Decoding of Short Codewords," IEEE Trans. CAS-II: Analog and Digital Signal Processing, 50(2), Feb. 2003, pp. 73-82.
10. L.Y. Liu, J.F. Wang, and J.Y. Lee, "CAM-based VLSI architecture for dynamic Hufiman coding," IEEE Trans. Consumer Electron., vol. 40, no. 3, pp. 282-289, Aug. 1994.
11. C.T. Hsieh and S. R Kim, "A Concurrent Memory-Efficient VLC Decoder for MPEG Applications," IEEE Trans. Consumer Electron., vol.42, pp. 439-446, Aug. 1996.
12. B.J. Shieh, et. al., "A New Approach of Group-Based VLC Codec System with Full Table Programmability," IEEE Trans. CAS for Video Tech., 11(2), Feb. 2001, pp. 210-221.
13. J.-S. Wang, et al., "An AND type match-line scheme for energy efficient content addressable memories" IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 464-465.