Adding instruction cache effect to schedulability analysis of preemptive real-time systems

Real-Time Technology and Applications - Proceedings

Volumn , Issue , 1996, Pages 204-212

  Busquets Mataix, Jose V ^a   Serrano, Juan J ^a   Ors, Rafael ^a   Gil, Pedro ^a   Wellings, Andy ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE PARTITIONING; EFFICIENT ANALYSIS; FIXED-PRIORITY SCHEDULERS; PREEMPTIVE SYSTEMS; SCHEDULABILITY ANALYSIS; SYSTEM CONFIGURATIONS; UNDERLYING SYSTEMS; WORST-CASE EXECUTION TIME;

CACHE MEMORY; INTERACTIVE COMPUTER SYSTEMS; BUFFER STORAGE; COMPUTER AIDED ANALYSIS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; RESPONSE TIME (COMPUTER SYSTEMS);

REAL TIME SYSTEMS;

PREEMPTIVE FIXED PRIORITY SCHEDULERS; PREEMPTIVE SYSTEMS; RATE MONOTONIC SCHEDULABILITY ANALYSIS (RMA); RESPONSE TIME SCHEDULABILITY ANALYSIS (RTA); WORST CASE EXECUTION TIME (WCET);

EID: 0029720109     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTTAS.1996.509537     Document Type: Conference Paper

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