메뉴 건너뛰기




Volumn 1, Issue , 2006, Pages

Disjunctive image computation for embedded software verification

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; GRAPH THEORY;

EID: 34047121643     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (17)
  • 2
    • 84947232436 scopus 로고
    • Bebop: A symboloc model checker for Boolean programs
    • Proc. of the SPIN Workshop SPIN'00
    • T. Ball and S. K. Rajamani. Bebop: A symboloc model checker for Boolean programs. In Proc. of the SPIN Workshop (SPIN'00), pages 113-130. LNCS 1885.
    • (1885) LNCS , pp. 113-130
    • Ball, T.1    Rajamani, S.K.2
  • 3
    • 34047147127 scopus 로고    scopus 로고
    • R. K. Ranjan, A. Aziz, R. K. Brayton, B. F. Plessier, and C. Fixley. Efficient BDD algorithms for FSM synthesis and verification. Presented at IWLS95, May 1995.
    • R. K. Ranjan, A. Aziz, R. K. Brayton, B. F. Plessier, and C. Fixley. Efficient BDD algorithms for FSM synthesis and verification. Presented at IWLS95, May 1995.
  • 4
    • 84947275334 scopus 로고
    • Border-block triangular form and conjunction schedule in image computation
    • Formal Methods in Computer Aided Design
    • I.-H. Moon, G. D. Hachtel, and F. Somenzi. Border-block triangular form and conjunction schedule in image computation. In Formal Methods in Computer Aided Design, pages 73-90. LNCS 1954.
    • (1954) LNCS , pp. 73-90
    • Moon, I.-H.1    Hachtel, G.D.2    Somenzi, F.3
  • 6
    • 84957376851 scopus 로고    scopus 로고
    • VIS: A system for verification and synthesis
    • Computer Aided Verification CAV'96
    • R. K. Brayton et al. VIS: A system for verification and synthesis. In Computer Aided Verification (CAV'96), pages 428-432. LNCS 1102.
    • LNCS , vol.1102 , pp. 428-432
    • Brayton, R.K.1
  • 9
    • 0030672545 scopus 로고    scopus 로고
    • Disjunctive partitioning and partial iterative squaring: An effective approach for symbolic traversal of large circuits
    • G. Cabodi, P. Camurati, L. Lavagno, and S. Quer. Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits. In Proc. of Design Automation Conference (DAC'97), pages 728-733.
    • Proc. of Design Automation Conference (DAC'97) , pp. 728-733
    • Cabodi, G.1    Camurati, P.2    Lavagno, L.3    Quer, S.4
  • 10
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Computers, C-35(8):677-691, 1986.
    • (1986) IEEE Trans. on Computers , vol.C-35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 11
    • 0035720870 scopus 로고    scopus 로고
    • Using a hardware model checker to verify software
    • Presented at
    • S. Edwards, T. Ma, and R. Damiano. Using a hardware model checker to verify software. Presented at Int. Conf. on ASIC, 2001.
    • (2001) Int. Conf. on ASIC
    • Edwards, S.1    Ma, T.2    Damiano, R.3
  • 12
    • 0030263395 scopus 로고    scopus 로고
    • Precise interprocedural dataflow analysis with applications to constant propagation
    • T. Reps, S. Horwitz, and M. Sagiv. Precise interprocedural dataflow analysis with applications to constant propagation. Theoretical Computer Science, 167:131-170, 1996.
    • (1996) Theoretical Computer Science , vol.167 , pp. 131-170
    • Reps, T.1    Horwitz, S.2    Sagiv, M.3
  • 13
    • 0142183308 scopus 로고    scopus 로고
    • Efficient symbolic model checking of software using partial disjunctive partitioning
    • Correct Hardware Design and Verification Methods CHARME'03
    • S. Barner and I. Rabinovitz. Efficient symbolic model checking of software using partial disjunctive partitioning. In Correct Hardware Design and Verification Methods (CHARME'03), pages 35-50. LNCS 2860.
    • LNCS , vol.2860 , pp. 35-50
    • Barner, S.1    Rabinovitz, I.2
  • 14
    • 26444468031 scopus 로고    scopus 로고
    • F-SOFT: Software verification platform
    • Computer-Aided Verification
    • F. Ivančić, Z. Yang, I. Shlyakhter, M. Ganai, A. Gupta, and P. Ashar. F-SOFT: Software verification platform. In Computer-Aided Verification, pages 301-306, 2005. LNCS 3576.
    • (2005) LNCS , vol.3576 , pp. 301-306
    • Ivančić, F.1    Yang, Z.2    Shlyakhter, I.3    Ganai, M.4    Gupta, A.5    Ashar, P.6
  • 16
    • 0030405069 scopus 로고    scopus 로고
    • Automatic state space decomposition for approximate FSM traversal based on circuit analysis
    • H. Cho, G. D. Hachtel, E. Macii, M. Poncino, and F. Somenzi. Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. on CAD, 15(12):1451-1464, 1996.
    • (1996) IEEE Trans. on CAD , vol.15 , Issue.12 , pp. 1451-1464
    • Cho, H.1    Hachtel, G.D.2    Macii, E.3    Poncino, M.4    Somenzi, F.5
  • 17
    • 0004030623 scopus 로고    scopus 로고
    • Multilevel algorithms for multi-constraint graph partitioning
    • Technical Report 98-019, University of Minnesota
    • G. Karypis and V. Kumar. Multilevel algorithms for multi-constraint graph partitioning. Technical Report 98-019, University of Minnesota, 1998.
    • (1998)
    • Karypis, G.1    Kumar, V.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.