Low-power 3D graphics processors for mobile terminals

IEEE Communications Magazine

Volumn 43, Issue 12, 2005, Pages 90-99

  Sohn, Ju Ho ^a   Park, Yong Ha ^a   Yoon, Chi Weon ^a   Woo, Ramchan ^a   Park, Se Jeong ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3D GRAPHICS; 3D GRAPHICS PROCESSOR; GRAPHICS ARCHITECTURE; LOW POWER; MOBILE 3D; MOBILE TERMINAL; PERFORMANCE REQUIREMENTS; POWER CONSUMPTION; PROTOTYPE DEVELOPMENT; SIMULATION ENVIRONMENT; SYSTEM RESOURCES;

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; COMPUTER TERMINALS; MOBILE PHONES;

THREE DIMENSIONAL;

EID: 34047107900     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2005.1561925     Document Type: Article

References (10)

1. J.-H. Sohn et al., "Optimization of Portable System Architecture for Real-time 3D Graphics," Proceedings of IEEE Int'l. Symp. Circuits Syst., 2002, pp. 1769-1772
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3. Y.-H. Park et al., "A 7.1GB/s Low Power Rendering Engine in 2D Array Embedded Memory Logic CMOS for Portable Multimedia System," IEEE J. Solid-State Circuits, vol.36, no.6, 2001, pp. 944-955
4. C.-W. Yoon et al., "A 80/20MHz 160mW Multimedia Processor Integrated with Embedded DRAM, MPEG4 and 3D Rendering Engine for Mobile Applications," IEEE J. Solid-State Circuits, vol.36, no.11, 2001, pp. 1758-1767
5. R. Woo et al., "A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications," IEEE J. Solid-State Circuits, vol. 39, no. 2, 2004, pp. 358-367
6. J.-H. Sohn et al., "A 50Mvertices/s Graphics Processor with Fixed-point Programmable Vertex Shader for Mobile Applications," IEEE Int'l. Solid-State Circuits Conf., 2005, pp. 192-193
7. J.-H. Sohn et al., "A Programmable Vertex Shader with Fixed-point SIMD Datapath for Low Power Wireless Applications," Proc. ACM Graphics Hardware Wksp., 2004, pp. 107-114
8. M. Kameyama et al., "3D Graphics LSI Core for Mobile Phone: Z3D," Proc. ACM Graphics Hardware Wksp., 2003, pp. 60-67.
9. M. Okabe et al., "A 90nm Embedded DRAM Single Chip LSI with a 3D Graphics, H.264 Codec Engine, and a Reconfigurable Processor," HotChips, vol.16, 2004.
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