A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 5, 2002, Pages 612-623

  Park, Se Jeong ^a   Kim, Jeong Su ^a   Woo, Ramchan ^a   Lee, Se Joong ^a   Lee, Kang Min ^a   Yang, Tae Hum ^b   Jung, Jin Yong ^b   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

3 D graphics; DRAM L2 cache; DRAM based SOC; Multilevel parallel cache; Texture cache

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); CACHE MEMORY; COMPUTER SIMULATION; COMPUTER WORKSTATIONS; DATA TRANSFER; DIGITAL FILTERS; DYNAMIC RANDOM ACCESS STORAGE; PIPELINE PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL COMPUTER GRAPHICS;

MULTILEVEL PARALLEL CACHE; SYSTEM ON CHIP DESIGN; TEXTURE CACHE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036564735     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.997855     Document Type: Article

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