High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 9, 2006, Pages 911-915

  Lin, Chih Hsiu ^a  

^a Andy) Wu, An Yeu   (Taiwan)

Author keywords

Decision feedback equalizer (DFE) gigabit system partial pre computation scheme two stage pre computation scheme; Index Terms

Indexed keywords

ADDERS; DIGITAL FILTERS; FEEDBACK; OPTICAL COMMUNICATION EQUIPMENT; PULSE AMPLITUDE MODULATION; VLSI CIRCUITS;

FEEDBACKWARD FILTER (FBF); GIGABIT SYSTEMS; MULTIPLEXERS;

DECISION FEEDBACK EQUALIZERS;

EID: 34047103351     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.881165     Document Type: Article

References (10)

1. K. K. Parhi, “Pipelining in algorithms with quantizer loops,” IEEE Trans. Circuits Syst., vol. 37, no. 7, pp. 745–754, Jul. 1991.
2. S. Kasturia and J. H. Winters, “Techniques for high-speed implementation of nonlinear cancellation,” IEEE J. Sel. Areas Commun., vol. 9, pp. 711-717,Jun. 1991.
3. P. M. Kogge, The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981.
4. K. K. Parhi and D. G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filter- Part I and II,” IEEE Trans. Acoust., Speech, Signal Process., vol. 37, no. 7, pp. 1099–1135, Jul. 1989.
5. J. I. Acha, “Computational structures for fast implementation of L-path and L-block digital filters,” IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 805–812, Jun. 1989.
6. L. E. Lucke and K. K. Parhi, “Parallel processing for rank order and stack filter,” IEEE Trans. Signal Process., no. 5, pp. 1178–1189, May 1994.
7. C. Leiserson, F. Rose, and J. Saxe, “Optimizing synchronous circuitry by retiming,” in Proc. 3rd Caltech Conf. VLSI, 1983, pp. 87–116.
8. 10GBASE-LX4, IEEE Std 802.3ae-2002, http://www.ieee802.org/3/ae.
9. K. K. Parhi, “Fast low-power VLSI binary addition,” in Proc. IEEE Int. Conf. Comput. Design (ICCD’97), Oct. 1997, pp. 676–684.
10. K. K. Parhi, “Pipelining of parallel multiplexer loops and decision feedback equalizers,” in Proc. IEEE Int. Conf. Acoust. Speech Signal Process. (ICASSP ’04), May 2004, vol. 5, pp. 17–21.