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Volumn 5, Issue , 2004, Pages

Pipelining of parallel multiplexer loops and decision feedback equalizers

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION TIME; ITERATION BOUND; MULTIPLEXER LOOPS; PARALLEL MULTIPLEXERS;

EID: 4544239088     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 0026171346 scopus 로고
    • Techniques for high-speed implementation of nonlinear cancellation
    • June
    • S. Kasturia and J. H. Winters, "Techniques for high-speed implementation of nonlinear cancellation," IEEE J. Select. Areas Commun., vol. 9, no. 5, pp. 711-717, June 1991.
    • (1991) IEEE J. Select. Areas Commun. , vol.9 , Issue.5 , pp. 711-717
    • Kasturia, S.1    Winters, J.H.2
  • 2
    • 0026186482 scopus 로고
    • Pipelining in algorithms with quantizer loops
    • July
    • K. K. Parhi, "Pipelining in algorithms with quantizer loops," IEEE Trans. on Circuits and Systems, vol. 37, no. 7, pp. 745-754, July 1991.
    • (1991) IEEE Trans. on Circuits and Systems , vol.37 , Issue.7 , pp. 745-754
    • Parhi, K.K.1
  • 4
    • 0344124984 scopus 로고
    • Concurrent cellular VLSI adaptive filter architectures
    • Oct.
    • K. K. Parhi and D. G. Messerschmitt, "Concurrent cellular VLSI adaptive filter architectures," IEEE Trans. Circuits Syst., vol. CAS-34, pp. 1141-1151, Oct. 1987.
    • (1987) IEEE Trans. Circuits Syst. , vol.CAS-34 , pp. 1141-1151
    • Parhi, K.K.1    Messerschmitt, D.G.2
  • 5
    • 0024700229 scopus 로고
    • Pipeline interleaving and parallelism in recursive digital filters, Part I and Part II
    • July
    • K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters, Part I and Part II," IEEE Trans. Acoust., Speech, Signal Processing, pp. 1099-1135, July 1989.
    • (1989) IEEE Trans. Acoust., Speech, Signal Processing , pp. 1099-1135
    • Parhi, K.K.1    Messerschmitt, D.G.2
  • 6
    • 0024716013 scopus 로고
    • Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck
    • Aug.
    • G. Fettweis and H. Meyr, "Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck," IEEE Trans. Commun., vol. 37, pp. 785-790, Aug. 1989.
    • (1989) IEEE Trans. Commun. , vol.37 , pp. 785-790
    • Fettweis, G.1    Meyr, H.2
  • 7
    • 0026981415 scopus 로고
    • A 140-Mb/s, 32-state, radix-4 Viterbi decoder
    • Dec.
    • P. J. Black and T. H. Meng, "A 140-Mb/s, 32-state, radix-4 Viterbi decoder," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1877-1885, Dec. 1992.
    • (1992) IEEE J. Solid-state Circuits , vol.27 , Issue.12 , pp. 1877-1885
    • Black, P.J.1    Meng, T.H.2
  • 9
    • 0024942358 scopus 로고
    • Look-ahead in dynamic programming and quantizer loops
    • May
    • K. K. Parhi, "Look-ahead in dynamic programming and quantizer loops," in Proc. IEEE Int. Symp. Circuits and Systems, pp. 1382-1387, May 1989.
    • (1989) Proc. IEEE Int. Symp. Circuits and Systems , pp. 1382-1387
    • Parhi, K.K.1
  • 10
    • 0033281193 scopus 로고    scopus 로고
    • Low-energy CSMT carry generators and binary adders
    • Dec.
    • K. K. Parhi, "Low-energy CSMT carry generators and binary adders," IEEE Trans. on VLSI Syst., vol. 7, no. 4, pp. 450-462, Dec. 1999.
    • (1999) IEEE Trans. on VLSI Syst. , vol.7 , Issue.4 , pp. 450-462
    • Parhi, K.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.