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Volumn 53, Issue 4, 2006, Pages 299-303

A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters

Author keywords

Analog digital (A D) conversion; calibration; timing

Indexed keywords

CALIBRATION; COMPUTER SIMULATION; DELAY CONTROL SYSTEMS; DIGITAL CONTROL SYSTEMS; JITTER; TIMING CIRCUITS;

EID: 33947594422     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.861887     Document Type: Article
Times cited : (41)

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  • 4
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    • A background comparator calibration technique for flash analog-to-digital converters
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    • C.-C. Huang and J.-T. Wu, “A background comparator calibration technique for flash analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1732–1740, Sep. 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.