Reliability of CSP interconnections under mechanical shock loading conditions

IEEE Transactions on Components and Packaging Technologies

Volumn 29, Issue 4, 2006, Pages 787-795

  Mattila, Toni T ^b   Marjamäki, Pekka ^b   Kivilahti, Jorma K ^a,b  

^a IEEE

^b AALTO UNIVERSITY   (Finland)

Author keywords

Chip scale package (CSP); Drop test; Finite element method (FEM); JESD22 B111; Lead free; Printed wiring board (PWB) coating; Reliability

Indexed keywords

FINITE ELEMENT METHOD; INTERCONNECTION NETWORKS; MULTILAYERS; RELIABILITY ANALYSIS; STATISTICAL METHODS; WEIBULL DISTRIBUTION;

DROP TEST; JESD22-B111; PRINTED WIRING BOARD (PWB) COATINGS; SHOCK LOADING;

CHIP SCALE PACKAGES;

EID: 33947194016     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2006.885948     Document Type: Article

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