NBTI reliability of strained SOI MOSFETs

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 2006, Issue , 2006, Pages 423-425

  Thareja, Gaurav ^a   Jack, Lee ^a   Thean, Aaron Voon Yew ^b   Vartanian, Victor ^b   Nguyen, Bich Yen ^b  

^a The University of Texas at Austin   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL DEVICES; CONSTANT VOLTAGE STRESS (CVS); NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); SUBTHRESHOLD SWING VALUES;

SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; TEMPERATURE MEASUREMENT; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 33847683297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Thean A.V. Y et al, "Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology," Symp VLSI Tech, 2005, pp. 134-135.
2. Schroder D.K. et al, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, (2003), pp. 1-18.
3. Rhee H.S. et al., "Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance boosters," IEDM 2005.
4. Bunyan R.J.T et al, "Activation of NBTI Degradation in SOI PMOS by Self-Heating," Int. SOI Conf., 1992, pp. 130-131.
5. Morifuji E. et al, "New considerations for highly reliable PMOSFETs in 100 nm generation and beyond," Symp VLSI Tech, 2001, pp. 117-118.
6. + polysilicon gate p-MOSFETs" IEEE Trans. Elec. Dev. Vol. 46, (1999), pp. 921-926.