Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 320-323

  Mukaida, Kenji ^a   Takenaka, Masahiko ^a   Torii, Naoya ^a   Masui, Shoichi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; CRYPTOGRAPHY; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; SMART CARDS; THEOREM PROVING;

HIGH-SPEED NETWORKS; MONTGOMERY MODULAR MULTIPLIERS; MULTIPLIER-ACCUMULATOR (MAC); RSA ALGORITHMS;

ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS;

EID: 4644232920     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. P. Montgomery, "Modular Multiplication without Trial Division, " Mathematics of Computation, vol. 44, no. 170, pp. 519-521, 1985
4. Ç. K Koç, "High-Speed RSA Implementation," Technical Report TR201, RSA Laboratories, 1994
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7. A. Satoh et al., "A Scalable Hardware Architecture for Elliptic Curve Cryptography on GF(p)," Proc. of IEICE A vol. J85-A, no. 11, pp.1624-1272, 2002 (Japanese)