Design guideline for halo condition on CMOSFETs utilizing FLA

Extended Abstracts of the Fifth International Workshop on Junction Technology, 2005

Volumn 2005, Issue , 2005, Pages 107-110

  Tsujii, H ^a   Adachi, K ^a   Ohuchi, K ^a   Aoki, N ^a   Ito, T ^b   Matsuo, K ^b   Suguro, K ^b   Ishimaru, K ^a   Ishiuchi, H ^a  

^a SoC Research and Development Center   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

CMOSFETS CHARACTERISTICS; DOPANTS; FLASH LAMP ANNEALING (FLA); HALO PROFILE DEPENDENCE;

MOSFET DEVICES;

EID: 33847288295     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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8. F. Ootsuka et al., IEDM Tech. Dig. (2003) p. 647.