Low frequency noise in multi-gate SOI CMOS devices

Solid-State Electronics

Volumn 51, Issue 2, 2007, Pages 292-298

  Zafari, Leily ^a   Jomaah, Jalal ^a   Ghibaudo, Gérard ^a  

^a IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

BACK GATE VOLTAGES; COUPLING EFFECT; DOUBLE GATE DEVICES; LOW FREQUENCY NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 33847263529     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.01.005     Document Type: Article

References (15)

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