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Volumn 2005, Issue , 2005, Pages 397-400

A new approach for real-time histogram equalization using FPGA

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DECODING; MACHINE DESIGN; OPTIMIZATION; REAL TIME SYSTEMS; STATISTICS;

EID: 33847231336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ispacs.2005.1595430     Document Type: Conference Paper
Times cited : (30)

References (7)
  • 1
    • 0033280732 scopus 로고    scopus 로고
    • IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework
    • Z. Salcic and J. Sivaswamy, "IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework," Real-Time Imaging, Vol.5, 1999, pp. 385-395.
    • (1999) Real-Time Imaging , vol.5 , pp. 385-395
    • Salcic, Z.1    Sivaswamy, J.2
  • 6
    • 0032305808 scopus 로고    scopus 로고
    • L. Xiying, N. Guqiang, C. Yanmei, P. Tian, and Z. Yanli, Real-time Image Histogram Equalization Using FPGA, Proc. Spie, Conf. 3561, 1998, pp. 293-299
    • L. Xiying, N. Guqiang, C. Yanmei, P. Tian, and Z. Yanli, "Real-time Image Histogram Equalization Using FPGA," Proc. Spie, Conf. Vol. 3561, 1998, pp. 293-299
  • 7
    • 0035770613 scopus 로고    scopus 로고
    • A DSP + FPGA based real-time histogram equalization system of infrared image
    • G. Dongsheng, Y. Nansheng, P. Defu, H. Min, S. Xiaoyan, and Z. Reolan, "A DSP + FPGA based real-time histogram equalization system of infrared image" Proc. Spie, Vol. 4602, 2001, pp.160-165.
    • (2001) Proc. Spie , vol.4602 , pp. 160-165
    • Dongsheng, G.1    Nansheng, Y.2    Defu, P.3    Min, H.4    Xiaoyan, S.5    Reolan, Z.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.