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Volumn 2, Issue , 2003, Pages 1009-1012

The hardware design of real-time infrared image enhancement system

Author keywords

[No Author keywords available]

Indexed keywords

BASIC PRINCIPLES; DSP+FPGA; GRAY LEVELS; GRAY-LEVEL; HARDWARE CIRCUITS; HARDWARE DESIGN; HUMAN EYE; IMAGE BRIGHTNESS; INFRARED IMAGE ENHANCEMENT; INFRARED IMAGE PROCESSING; INFRARED IMAGES; LOW CONTRAST; MAIN CHARACTERISTICS; REAL-TIME IMAGE ENHANCEMENT;

EID: 78549241850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICNNSP.2003.1281039     Document Type: Conference Paper
Times cited : (10)

References (6)
  • 1
    • 0032374257 scopus 로고    scopus 로고
    • Very low cost real time histogram based contrast enhancer utilizing fixed-point DSP processing
    • McCaffrey N J et al, "Very low cost real time histogram based contrast enhancer utilizing fixed-point DSP processing," SPIE. 3303, pp36-43. 1998.
    • (1998) SPIE , vol.3303 , pp. 36-43
    • McCaffrey, N.J.1
  • 2
    • 78650098554 scopus 로고    scopus 로고
    • High density FPGAs for real-time video processing
    • Steve Nordhau ser, "High Density FPGAs for real-time Video Processing. SPIE. Vol. 3028. 0277-786X, 1997.
    • (1997) SPIE , vol.3028
    • Ser, S.N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.