Instruction folding for an asynchronous Java co-processor

2005 International Symposium on System-on-Chip, Proceedings

Volumn 2005, Issue , 2005, Pages 18-21

  Säntti, Tero ^a   Plosila, Juha ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER APPLICATIONS; EMBEDDED SYSTEMS; INTERFACES (COMPUTER); JAVA PROGRAMMING LANGUAGE; SIGNAL PROCESSING; SYSTEMS ANALYSIS;

INSTRUCTION DECODING; JAVA EXECUTION; SYSTEM-ON-CHIP (SOC);

PROGRAM PROCESSORS;

EID: 33847182086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/issoc.2005.1595633     Document Type: Conference Paper

References (8)

1. E. Gagnon. "A Portable Research Framework for the Execution of Java Bytecode", Ph.D. thesis, School of Computer Science, McGill University, Montreal, 2002.
2. J. Hennessy and D. Patterson. "Computer Architecture: a Quantitative Approach", Second Edition, Morgan Kaufmann Publishers, Inc., 1996.
3. Z. Liang, J. Plosila, and K. Sere, "Asynchronous Java Accelerator for Embedded Java Virtual Machine", In Proc. of IEEE CAS Symposium on Emerging Technologies, Frontiers of Mobile and Wireless Communication, Shanghai, China, June 2004.
4. P. Liljeberg, J. Plosila, and J. Isoaho. "Self-Timed Communication Platform for Implementing High-Performance Systems-on-Chip", the VLSI Integration Journal 38, Elsevier, 2004.
5. T. Lindholm and F. Yellin. "The Java Virtual Machine Specification", Second Edition, Addison-Wesley, 1997.
6. J. Sparso and S. Furber. "Principles of Asynchronous Circuit Design - A System Perspective", Kluwer Academic Publishers, 2001.
7. T. Säntti and J. Plosila. "Communication Scheme for an Advanced Java Co-Processor", In Proc. IEEE Norchip 2004, Oslo, Norway, November 2004.
8. T. Säntti and J. Plosila. "Architecture for an Advanced Java Co-Processor", In Proc. International Symposium on Signals, Circuits and Systems 2005, lasi, Romania, July 2005.