Architecture for an advanced java co-processor

ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings

Volumn 2, Issue , 2005, Pages 501-504

  Säntti, Tero ^a   Plosila, Juha ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; INTEGRATED CIRCUITS; JAVA PROGRAMMING LANGUAGE; PIPELINE PROCESSING SYSTEMS;

CPU; JAVA BYTECODE; JAVA CO-PROCESSOR;

MICROPROCESSOR CHIPS;

EID: 33749066310     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCS.2005.1511287     Document Type: Conference Paper

References (6)

1. I. Hennessy and D. Patterson, "Computer Architecture: a Quantitative Approach", Second Edition, Morgan Kaufmann Publishers, Inc., 1996.
2. Z. Liang, J. Plosila, and K. Sere. "Asynchronous Java Accelerator for Embedded Java Virtual Machine", In Proc. of IEEE CAS Symposium on Emerging Technologies, Frontiers of Mobile and Wireless Communication. Shanghai, China, June 2004.
3. P. Liljeberg, J. Plosila, and J. Isoaho. "Self-Timed Communication Plat-form for Implementing High-Performance Systems-on-Chip", the VLSI Integration Journal 38. Elsevier, 2004.
4. T. Lindholm and F. Yellin. "The Java Virtual Machine Specification", Second Edition, Addison-Wesley, 1997.
5. I. Sparso and S. Furber, "Principles of Asynchronous Circuit Design - A System Perspective", Kluwer Academic Publishers, 2001.
6. T. Säntti and J. Plosila, "Communication Scheme for an Advanced Java Co-Processor", In Proc. Norchip 2004. Oslo. Norway, November 2004.