A 1.0V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 395-398

  Ishii, Hirotomo ^a   Tanabe, Ken ^a   Iida, Tetsuya ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; THERMAL NOISE; VOLTAGE CONTROL;

DECOUPLING CAPACITORS; POWER CONSUMPTION; REFERENCE VOLTAGES;

ANALOG TO DIGITAL CONVERSION;

EID: 33847169930     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568688     Document Type: Conference Paper

References (7)

1. B. Hemes, A. Briskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud, and Ø. Moldsvor, "A 1.2V 220MS/S 10b pipeline ADC implemented in 0. 13μm digital CMOS," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 256257.
2. O. Stroeble, V. Dias, and C. Schwoerer, "An 80MHz 10b pipeline ADC with dynamic range doubling and dynamic reference selection," in ISSCC Dig. Tech, Papers, Feb. 2004, pp. 462-463.
3. M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, "A 10b 125MS/S 40mW pipelined ADC in 0.18μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 282-283.
4. W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. Solid-State Circuits, vol. 36, pp. 1931-1936, Dec. 2001.
5. M. Dessouky and A. Kaiser, "Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping," IEEE J. Solid-State Circuits, vol. 36, pp. 349-355, Mar. 2001.
6. J. Goes, J. C. Vital, and J. Franca, Systematic Design for Optimisation of Pipelined ADCs. Boston: Kluwer Academic Publishers, 2001.
7. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.