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Volumn 2006, Issue , 2006, Pages

A distributed object system approach for dynamic reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; SOFTWARE ENGINEERING;

EID: 33847167185     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639448     Document Type: Conference Paper
Times cited : (10)

References (7)
  • 1
    • 85033339426 scopus 로고    scopus 로고
    • Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation
    • Leuven, Belgium, August
    • A. Bartic et al. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. In FPL 2004, Leuven, Belgium, August 2004.
    • (2004) FPL 2004
    • Bartic, A.1
  • 2
    • 33746933468 scopus 로고    scopus 로고
    • Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
    • Tampere, Finland, August
    • R. Hecht, S. Kubisch, A. Herrholz, and D. Timmermann. Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs. In FPL 2005, pages 527-530, Tampere, Finland, August 2005.
    • (2005) FPL 2005 , pp. 527-530
    • Hecht, R.1    Kubisch, S.2    Herrholz, A.3    Timmermann, D.4
  • 3
    • 85033346285 scopus 로고    scopus 로고
    • Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores
    • Denver, Colorado, USA, April
    • M. Hühner, K. Paulsson, and J. Becker. Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. In RAW 2005, Denver, Colorado, USA, April 2005.
    • (2005) RAW 2005
    • Hühner, M.1    Paulsson, K.2    Becker, J.3
  • 4
    • 85033347308 scopus 로고    scopus 로고
    • Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs. In ARCS 2005
    • Innsbruck, Austria, March, GI
    • M. Hübner, K. Paulsson, M. Stitz, and J. Becker. Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs. In ARCS 2005, Workshops Proceedings, LNI, Innsbruck, Austria, March 2005. GI.
    • (2005) Workshops Proceedings, LNI
    • Hübner, M.1    Paulsson, K.2    Stitz, M.3    Becker, J.4
  • 5
    • 0345855931 scopus 로고    scopus 로고
    • Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs
    • Montpellier, France, September
    • T. Marescaux et al. Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs. In FPL 2002, Montpellier, France, September 2002.
    • (2002) FPL 2002
    • Marescaux, T.1
  • 6
    • 84947926905 scopus 로고    scopus 로고
    • A runtime environment for reconfigurable hardware operating systems
    • Leuven, Belgium, August
    • H. Walder and M. Platzner. A runtime environment for reconfigurable hardware operating systems. In FPL 2004, pages 831-835, Leuven, Belgium, August 2004.
    • (2004) FPL 2004 , pp. 831-835
    • Walder, H.1    Platzner, M.2
  • 7
    • 85033340431 scopus 로고    scopus 로고
    • Research Isssues in Operating Systems for Reconfigurable Computing
    • Las Vegas, Nevada, USA, June
    • G. Wigley and D. Kearney. Research Isssues in Operating Systems for Reconfigurable Computing. In ERSA '02, Las Vegas, Nevada, USA, June 2002.
    • (2002) ERSA '02
    • Wigley, G.1    Kearney, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.