Using design patterns to overcome image processing constraints on FPGAs

Proceedings - Third IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2006

Volumn 2006, Issue , 2006, Pages 47-53

  Gribbon, K T ^a   Bailey, D G ^a   Johnston, C T ^a  

^a MASSEY UNIVERSITY   (New Zealand)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROBLEM SOLVING;

HARDWARE CONSTRAINTS; MAPPING PROCESS; REAL-TIME OBJECT TRACKING;

IMAGE PROCESSING;

EID: 33847108917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2006.93     Document Type: Conference Paper

References (17)

1. Hutchings, B. and Villasenor, J., "The Flexibility of Configurable Computing," IEEE Signal Processing Magazine, vol. 15, pp. 67-84, Sep, 1998.
2. Downton, A. and Crookes, D., "Parallel Architectures for Image Processing," IEE Electronics & Communication Engineering Journal, vol. 10, pp. 139-151, Jun, 1998.
3. Gribbon, K. T. and Bailey, D. G., "A Novel Approach to Real-time Bilinear Interpolation," Second IEEE International Workshop on Electronic Design, Test and Applications, Perth, Australia, pp. 126-131, Jan, 2004.
4. Gribbon, K. T., Johnston, C. T., and Bailey, D. G., "A Real-time FPGA Implementation of a Lens Distortion Correction Algorithm with Bilinear Interpolation," Proc. Image and Vision Computing New Zealand, Massey University, Palmerston North, New Zealand, pp. 408-413, Nov, 2003.
5. Najjar, W. A., Böhm, W., Draper, B. A., Hammes, J., Rinker, R., Beveridge, J. R., Chawathe, M., and Ross, C., "High-level language abstraction for reconfigurable computing," IEEE Computer, vol. 36, pp. 63-69, Aug, 2003.
6. Haldar, M., Nayak, A., Choudhary, A., and Banerjee, P., "A system for synthesizing optimized FPGA hardware from MATLAB," Proc. International Conference on Computer-aided Design, San Jose, California, pp. 314-319, 2001.
7. Webb, J. A., "Steps toward architecture-independent image processing," IEEE Computer, vol. 25, no. 2, pp. 21-31, 1992.
8. Alston, T. and Madahar, B., "From C to netlists: hardware engineering for software engineers?" IEE Electronics & Communication Engineering Journal, pp. 165-173, Aug, 2002.
9. Offen, R. J. VLSI Image Processing, London: Collins, 1985.
10. Johnston, C. T., Gribbon, K. T., and Bailey, D. G., "Implementing Image Processing Algorithms on FPGAs," Proc. Eleventh Electronics New Zealand Conference, Palmerston North, New Zealand, pp. 118-123, Nov. 2004.
11. Gamma, E., Helm, R., Johnson, R., and Vlissides, J. Design Patterns: Elements of Reusable Object-Oriented Software, United States of America: Addison-Wesley Publishing Company, 1995.
12. Alexander, C., Ishikawa, S., Silverstein, M., Jacobsen, M., Fiksdahl-King, I., and Angel, S. A Pattern Language, New York: Oxford University Press, 1977.
13. Benkrid, K., Crookes, D., and Benkrid, A., "Towards a general framework for FPGA based image processing using hardware skeletons," Parallel Computing, vol. 28, pp. 1141-1154, Aug, 2002.
14. DeHon, A., Adams, J., DeLorimier, M., Kapre, N., Matsuda, Y., Naeimi, H., Vanier, M., and Wrighton, M., "Design patterns for reconfigurable computing," 12th Annual IEEE Symp. Field-Programmable Custom Computing Machines, pp. 13-23, 2004.
15. Johnston, C. J., Gribbon, K. T., and Bailey, D. G., "FPGA-based Remote Object Tracking for Real-time Control," To appear in Proc. First International Conference on Sensing Technology, Nov, 2005.
16. Sen Gupta, G. and Bailey, D. G., "A new colour-space for efficient and robust segmentation," Proc. Image and Vision Computing New Zealand, Christchurch, New Zealand, pp. 315-320, Nov, 2004.
17. Russ, J. C. The Image Processing Handbook, Boca Raton, Florida: CRC Press, 2002.