A 1.2-V, 12-bit, 200MSample/s current-steering D/A converter in 90-nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 747-750

  Ueno, Takeshi ^a   Yamaji, Takafumi ^a   Itakura, Tetsuro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MOBILE TELECOMMUNICATION SYSTEMS; MODULATORS; VOLTAGE CONTROL;

CMOS TECHNOLOGY; SPURIOUS FREE DYNAMIC RANGE (SFDR); SUPPLY VOLTAGE; VOLTAGE DROP;

DIGITAL TO ANALOG CONVERSION;

EID: 33847106899     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568776     Document Type: Conference Paper

References (5)

1. Takahiro Miki, Yasuyuki Nakamura, Masao Nakaya, Sotoju Asai, Yoichi Akasaka and Yasutaka Horiba, "An 80-MHz 8-bit CMOS D/A converter," IEEE Journal of Solid-State Circuits, vol. sc-21, no. 6, pp. 983-988, Dec. 1986.
2. Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh and Nobuharu Yazawa, "A 10-b 70MS/S CMOS D/A converter," IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 637-642, Apr. 1991.
3. Yonghua Cong and Randall L. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Transactions on Circuits and Systems II, vol. 47, no. 7, pp. 585-595, Jul. 2000.
4. Geert A. M. Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert and Georges G. E. Gielen, "A 14-bit intrinsic accuracy Q2RandomWalk CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
5. 2" IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.