Mapping a multiple antenna SDM-OFDM receiver on the ADRES coarse-grained reconfigurable processor

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2005, Issue , 2005, Pages 473-478

  Novo, David ^a   Moffat, Will ^a   Derudder, Veerle ^a   Bougard, Bruno ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONFORMAL MAPPING; DIGITAL SIGNAL PROCESSING; PROGRAM PROCESSORS; RECEIVING ANTENNAS; SPACE DIVISION MULTIPLE ACCESS; VERY LONG INSTRUCTION WORD ARCHITECTURE; WIRELESS TELECOMMUNICATION SYSTEMS;

COARSE GRAIN RECONFIGURABLE ARRAYS (CGRA); SOFTWARE DEFINED RADIO (SDR); SPACE DIVISION MULTIPLEXING (SDM);

ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

EID: 33846983880     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2005.1579915     Document Type: Conference Paper

References (10)

1. Reiner Hartenstein. A decade of reconfigurable computing: a visionary retrospective. In Proc. of Design, Automation and Test in Europe (DATE), 2001.
2. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, and Rudy Lauwereins. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Proc. of Field-Programmable Logic and Applications, 2003.
3. M. Wouters. An Approach for Real Time Prototyping of MIMO-OFDM Systems. EUSIPCO 2004.
4. Bingfeng Mei, Serge Vemalde, Diederik Verkest, Hugo De Man, and Rudy Lauwereins. DRESC: A retargetable compiler for coarse-grained reconfigurable architectures. In Proc. of International Conference on Field Programmable Technology, pages 166-173, 2002.
5. Monica S. Lam. Software pipelining: an effecive scheduling technique for VLIW machines. In Proc. of ACM SIGPLAN'88 Conference on Programming Language Design and Implementation, pages 318-327, 1988.
6. P. Vandenameele, A combined OFDM/SDMA approach, Journal on Selected Areas in Communications, Vol. 18, No. 11, November 2000
7. The MathWorks. http://www.mathworks.com
8. Bingfeng Mei, Serge Vemalde, Diederik Verkest, Hugo De Man, and Rudy Lauwereins. Exploiting loop-level parallelism for coarse-grained reconfigurable architecture using modulo scheduling. IEE Proceedings: Computer and Digital Techniques, 150(5), September 2003.
9. The IMPACT group, http://www.crhc.uiuc.edu/impact.
10. H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, "Morphosys: an integrated reconfigurable system for data-parallel and computation-intensive applications," IEEE Trans. on Computers, vol. 49, pp. 465-481, May 2000.