Efficient motion vector refinement architecture for sub-pixel motion estimation systems

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2005, Issue , 2005, Pages 313-318

  Dias, Tiago ^a   Roma, Nuno ^a   Sousa, Leonel ^a  

^a INSTITUTO SUPERIOR DE ENGENHARIA DE LISBOA   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; IMAGE PROCESSING; INTERPOLATION; OPTIMIZATION; REAL TIME SYSTEMS; VECTOR QUANTIZATION; VLSI CIRCUITS;

CONFIGURABLE MOTION ESTIMATION; INTERPOLATION ALGORITHM; SUB PIXEL MOTION ESTIMATION; VLSI ARCHITECTURE;

MOTION ESTIMATION;

EID: 33846972962     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2005.1579885     Document Type: Conference Paper

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