The sum-absolute-difference motion estimation accelerator

Proceedings - 24th EUROMICRO Conference, EURMIC 1998

Volumn 2, Issue , 1998, Pages 559-566

  Vassiliadis, S ^a   Hakkennes, E A ^a   Wong, J S S M ^a   Pechanek, G G ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b BOPS Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSOLUTE VALUES; MACHINE CYCLE; MEAN ABSOLUTE DIFFERENCES; MOTION ESTIMATION ACCELERATORS; SINGLE VECTORS; SUM ABSOLUTE DIFFERENCES;

MOTION ESTIMATION;

EID: 85046952799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1998.708071     Document Type: Conference Paper

References (19)

1. N. Ahmed, T. Natarajan, and K. Rao. Discrete cosine transform. IEEE Transactions on Computers, pages 9C-93, jan 1974.
2. L. Dadda. Some schemes for parallel multipliers. Alta Frequenza, 34:343-356, May 1965.
3. B. Furht, J. Greenberg, and R. Westwater. Motion Estimation Algorithms for Video Compression. Kluwer Academic Publishers, 1997.
4. D. L. Gall. Mpeg: A video compression standard for multimedia applications. Communications of the ACM, 34(4):44-58, April 1991.
5. J. R. Jain and A. K. Jain. Displacement measurement and its applications in interframe image coding. IEEE Transactions on Communications, COM-29( 12): 179-808, December 198 l.
6. S. Kappagantula and K. Rao. Motion compensated predictive coding. In Proc. Int. Tech. Symp. SPJE, San Diego, CA, August 1983.
7. H. Kitjima. A symmetrric cosine transform. IEEE Transactions on Computers, c-29(4):317-323, april 1980.
8. T. Koga, K. Linuma, A. Hirano, Y.Iijima, and T. Ishiguro. Motion-compensated interframe coding for video conferencing. In NTC 81 Proc., pages G5.3.1-5, New Orleans, LA, December 1981.
9. R. Lim. High-speed multiplication and multiple summand addition. In Proc. IEEE 4thSymp. Com. Arithmetic, pages 145-153, October 1978.
10. J. L. Mitchell, W. B. Pennebaker, C. E. Fogg, and D. J. LeGall. MPEG Video Compression Standard. Digital Multimedia Standard Series. Chapman and Hall, 1996.
11. R. Montoye, E. Hokenek, and S. Runyon. Design of the IBM RISC System/6000 floating-point execution unit. IBM Journal of Research and Development, 34( 1):59-70, January 1990.
12. A. N. Netravali and B. G. Haskell. Digital Pictures; Representation, Compression, and Standards. Plenum Press, 1994.
13. P. Song and G. De Michelli. Circuits and architecture tradeoffs for high-speed multiplication. JEEE Journal of Solid-State Circuits, SC-26(9):1184-1198, 1991.
14. R. Srinivasan and K. Rao. Predictive coding based on motion estimation. IEEE Transactions on Communicatios, COM-33:1011-1014, September 1985.
15. B. Tseng and W. Miller. On computing the discrete cosine transform. IEEE Transactions on Computers, c-27( 10):966-968, Oct 1978.
16. S. Vassiliadis, J: Hoekstra, and H.-T. Chiu. Array multiplication scheme using (p,2) counters and pre-addition. Electronics Letters, 31(8):619420, April 1995.
17. S. Vassiliadis, E. M. Schwarz, and D. J. Hanrahan. A general proof of overlapped multiple-bit scanning multiplications. IEEE Transactions on Computers, 38(2): 172-183, February 1989.
18. S. Vassiliadis, E. M. Schwarz, and B. M. Sung. Hard-wired multipliers with encoded partial products. IEEE Transactions on Computers, 40(11): 1181-1197, November 1991.
19. C. Wallace. A suggestion for parallel multipliers. IEEE Trans. Electron. Comput., EC-13: 14-17, 1964