An efficient reconfigurable multiplier architecture for Galois field GF(2m)

Microelectronics Journal

Volumn 34, Issue 10, 2003, Pages 975-980

  Kitsos, P ^a   Theodoridis, G ^a   Koufopavlou, O ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

All one polynomial; Bit serial; Cryptography; Elliptic curves; Galois field; Irreducible polynomial; Linear Feedback Shift Register; Low power; Polynomial multiplication

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; CRYPTOGRAPHY; POLYNOMIALS; SHIFT REGISTERS;

LINEAR FEEDBACK SHIFT REGISTERS;

MICROELECTRONICS;

EID: 0141620308     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(03)00172-1     Document Type: Conference Paper

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