Low complexity bit-parallel multipliers based on a class of irreducible pentanomials

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 12, 2006, Pages 1388-1393

  Imaña, José Luis ^a   Hermida, Román ^a   Tirado, Francisco ^a  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Canonical basis; Galois fields; Irreducible pentanomials; Matrix decomposition; Multiplication

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CRYPTOGRAPHY; PARAMETER ESTIMATION; POLYNOMIALS;

CANONICAL BASIS; GALOIS FIELDS; IRREDUCIBLE PENTANOMIALS; MATRIX DECOMPOSITION; MULTIPLICATION;

MULTIPLYING CIRCUITS;

EID: 33846634589     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.887835     Document Type: Article

References (7)

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