FEM-based method to determine mechanical stress evolution during process flow in microelectronics, application to stress-voiding

Microelectronics Reliability

Volumn 47, Issue 2-3, 2007, Pages 295-301

  Orain, S ^a   Barbe J C ^b   Federspiel, X ^a   Legallo, P ^c   Jaouen, H ^d  

^a PHILIPS RESEARCH LABORATORIES   (Germany)

^b CEA LETI   (France)

^c CEA GRENOBLE   (France)

^d STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; OPTIMIZATION; SHRINKAGE; STRESS ANALYSIS; VLSI CIRCUITS;

MATERIAL DEPOSITION; MECHANICAL STRESS; STRESS-VOIDING; THERMAL RAMPING STEPS;

MICROELECTRONIC PROCESSING;

EID: 33846598911     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.09.018     Document Type: Article

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