Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 134-142

  Maezawa, M ^a   Kurosawa, I ^a   Kameda, Y ^b   Nanya, T ^b  

^a Electrotechnical Laborator   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CROSSBAR EQUIPMENT; DELAY CIRCUITS; JOSEPHSON JUNCTION DEVICES; LOGIC GATES; LOW POWER ELECTRONICS; QUANTUM OPTICS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS LOGIC; DUAL-RAIL LOGIC; HIGH SPEED; LOGIC DELAYS; LOW POWER; RAPID SINGLE FLUX QUANTUM CIRCUITS; RAPID SINGLE-FLUX QUANTUM;

COMPUTER CIRCUITS;

EID: 0004898277     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494445     Document Type: Conference Paper

References (16)

1. A. Barone and G. Paterno, Physics and Applications of the Josephson Effects. John Wiley and Sons, 1982.
2. J. Z. Deng, S. R. Whiteley, and T. Van Duzer, "Data- driven self-timing of RSFQ digital integrated circuits," in Extended Abstracts of ISEC'95, pp. 189-191, Sep. 1995.
3. C. A. Hamilton and K. C. Gilbert, "Margins and yield in single flux quantum logic," IEEE Trans. Appl. Superconduct., vol. 4, pp. 157-163, Dec. 1991.
4. Y. Kameda and T. Nanya, "A gate model and circuit structure for pulse-driven asynchronous circuits," Technical Report of IEICE FTS94-25, Apr. 1994. (in Japanese)
5. H. Kroger and U. Ghoshal, "Can superconductive digital systems compete with semiconductor systems?," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2307-2314, Mar. 1993.
6. I. Kurosawa, H. Nakagawa, M. Aoyagi, S. Kosaka, and S. Takada, "A fully operational 1-kb variable threshold Josephson RAM," IEEE J. of Solid-State Circuits, vol. 26, pp. 572-577, Apr. 1991.
7. I. Kurosawa, H. Nakagawa, M. Aoyagi, M. Maezawa, Y. Kameda, and T. Nanya, "A basic circuit for asynchronous superconductive logic using RSFQ gates," in Extended Abstracts of ISEC'95, pp. 204-206, Sep. 1995.
8. K. K. Likharev, Dynamics of Josephson Junctions and Circuits. Gordon and Breach, 1986.
9. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: a new Josephson-junction technology for sub-teraherz-clock-frequency digital systems," IEEE Trans. Appl. Superconduct., vol. 1, pp. 3-28, Mar. 1991.
10. O. A. Mukhanov, S. V. Rylov, V. K. Semenov, and S. V. Vyshenskii, "RSFQ logic arithmetic," IEEE Trans. Magnetics, vol. 25, pp. 857-860, Mar. 1989.
11. O. A. Mukhanov, P. D. Bradley, S. B. Kaplan, S. V. Rylov, and A. F. Kirichenko, "Design and operation of RSFQ circuits for digital signal processing," in Extended Abstracts of ISEC'95, pp. 27-30, Sep. 1995.
12. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380 ps, 9.5 mW Josephson 4-Kbit RAM operating at a high bit yield," IEEE Trans. Appl. Superconduct. vol. 5, pp. 2447-2452, June. 1995.
13. A. C. Rose-Innes and E. H. Rhoderick, Introduction to Superconductivity. Pergamon, 1978.
14. C. Seitz, "System timing," in C. Mead and L. Conway, Introduction to VLSI systems. Addison-Wesley, 1980.
15. H. Weinstock and R. W. Ralston (eds.), The new superconducting electronics. Kluwer Academic Publishers, 1993.
16. P. F. Yuh, "A 2-Kbit superconducting memory chip," IEEE Trans. Appl. Superconduct., vol. 3, pp. 30133012, June 1991.