Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs

Proceedings of the International Symposium on System Synthesis

Volumn Part F129194, Issue , 1999, Pages

  Horstmannshoff, Jens ^a   Meyr, Heinrich ^a  

^a Integrated Signal Processing Systems   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDINGS; CODES (SYMBOLS); COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA TRANSFER; HIGH LEVEL SYNTHESIS; POLYNOMIAL APPROXIMATION;

ARBITRARY PATTERNS; BEHAVIORAL SYNTHESIS; BUILDING BLOCK-BASED DESIGNS; HIGH LEVEL BUILDING BLOCKS; NON-MATCHING INTERFACE; OPTIMIZED SYSTEM; POLYNOMIAL TIME COMPLEXITY; SYNCHRONOUS DATA FLOW;

DATA FLOW ANALYSIS;

EID: 84949971975     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1999.814258     Document Type: Conference Paper

References (11)

1. R. Camposano. A review of hardware synthesis techniques-behavioral synthesis. In G. D. Micheli, editor, Hardware/Software Co-Design, 1996.
2. J. Horstmannshoff, T. Grötker, and H. Meyr. Mapping Mul-tirate Dataflow to Complex RT Level Hardware Models. In ASAP. IEEE, 1997.
3. M. Hunt and J. Rowson. Blocking in a system on a chip. IEEE Spectrum, November 1996.
4. H. Jagadish and T. Kailath. Obtaining Schedules for Digital Systems. IEEE Transactions on Signal Processing, 39, November 1991.
5. E. Lawler. Combinatorial Optimization: Networks and Ma-troids. Rinehart & Winston, 1976.
6. E. Lee and D. Messerschmitt. Synchronous data flow. Proceedings of the IEEE, September 1987.
7. C. Leiserson, F. Rose, and J. Saxe. Optimizing Synchronous Circuitry by Retiming. In Proceedings of the 3rd Caltech Conference on VLSI, pages 87-116. ACM, 1991.
8. H. Meyr, M. Moeneclaey, and S. Fechtel. Digital Communication Receivers. John Wiley and Sons, 1998.
9. SYNOPSYS. COSSAP Block Diagram Editor Users Guide, 1999.
10. M. C. Williamson and E. A. Lee. Synthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications. November 3-6 1996.
11. P. Zepter, T. Grötker, and H. Meyr. Digital Receiver Design using VHDL Generation from Data Flow Graphs. In Proc. 32nd Design Automation Conf., June 1995.