How detrimental could a via be?

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2004, Pages 91-94

  Shan, Lei ^a   Kwark, Young ^a   Dreps, Daniel ^a   Trewhella, Jean ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RATES; FAR-END CROSSTALK (FEXT); PLATED THROUGH HOLES (PTH); SYSTEM PERFORMANCE;

COMPUTER HARDWARE; COMPUTER SIMULATION; CROSSTALK; ELECTRIC LINES; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; NOTCH FILTERS; PRINTED CIRCUIT BOARDS; SIMULATORS;

OPTICAL INTERCONNECTS;

EID: 15944383086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. G. S. Kanter, A. K. Samal, O. Coskun and A. Gandhi, "Electronic equalization for enabling communications at OC-192 rates using OC-48 components", 25 August 2003, Vol. 11, No. 17, OPTICS EXPRESS 2029
2. G. Edlund, Y. Kwark, C. Schuster, and L. Shan, "Developing a Working Model for Vias", DesignCon 2004, San Jose, Feb 2004.