Laminate package trends for high-speed system interconnects

Electrical Performance of Electronic Packaging

Volumn , Issue , 2003, Pages 147-150

  Cases, M ^a   De Araujo, D N ^a   Pham, N ^a   Blackshear, E ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCE; ELECTRIC POWER TRANSMISSION; ELECTRONICS PACKAGING;

DESIGN TRADEOFF; HIGH SPEED SYSTEMS; HIGH-SPEED DEVICES; HIGH-SPEED SIGNALING; IN-PROCESS TECHNOLOGY; PACKAGING SOLUTIONS; POWER DELIVERY; SIGNAL INTEGRITY;

PACKAGING;

EID: 33845883861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2003.1250019     Document Type: Conference Paper

References (7)

1. G. Frantz, "Digital Signal Processor Trends, " IEEE Micro, Volume 20, Issue 6, Nov.-Dec. 2000, pp 52-59.
2. G. A. Katopis, "Operating Frequency Trends for High Performance Off-Chip Buses, " Electrical Performance of Electronic Packaging Meeting, pp 37-41, October 1999.
3. R. Shukla, V. Murali, A. Bhansali, "Flip Chip CPU Package Technology at Intel: A Technology and Manufacturing Overview, " Electronic Components and Technology Conference, pp 945-949, May 1999.
4. V. K. Nagesh, R. Peddada, R. Ramalingam, B. Sur, A. Tai, "Challenges of Flip Chip on Organic Substrate Assembly Technology, " Electronic Components and Technology Conference, pp 975-978, May 1999.
5. H. Braunisch, S. N. Towle, R. D. Emery, C. Hu, G. J. Vandentop, "Electrical Performance of Bumpless Buildup Layer Packaging, " Electronic Components and Technology Conference, pp 353-358, May 2002.
6. Prismark Partners LLC, "Business Opportunities Resulting from Regional and Technology Shifts in Package Substrate Fabrication, " Japan Printed Circuits Association Meeting, June 2002.
7. D. N. deAraujo, M. Cases, N. Pham, B. Rubin, "Substrate Design Optimization for High Speed Links, " Electronic Components and Technology Conference, pp 1419-1424, May 2003.