A 50 power reduction in H.264/AVC HDTV video decoder LSI by dynamic voltage scaling in elastic pipeline

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E89-A, Issue 12, 2006, Pages 3642-3651

  Kawakami, Kentaro ^a   Takemura, Jun ^b   Kuroda, Mitsuhiko ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a  

^a KOBE UNIVERSITY   (Japan)

^b KANAZAWA UNIVERSITY   (Japan)

Author keywords

Divided entropy decoder; DVS (dynamic voltage scaling); Elastic pipeline; H.264 AVC; Low power

Indexed keywords

CONTEXT SENSITIVE LANGUAGES; DECODING; HIGH DEFINITION TELEVISION; LOGIC CIRCUITS; POWER CONTROL; SYNTACTICS;

DIVIDED ENTROPY DECODERS; DYNAMIC VOLTAGE SCALING (DVS); ELASTIC PIPELINES; SYNTAX ELEMENT DECODING (SED);

LSI CIRCUITS;

EID: 33845572283     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e89-a.12.3642     Document Type: Article

References (12)

1. K.J. Nowka, G.D. Carpenter, E.W. MacDonald, H.C. Ngo, B.C. Brock, K.I. Ishii, T.Y. Nguyen, and J.L. Burns, "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol.37, no.11, pp.1441-1447, Nov. 2002.
2. H. Ohira, K. Kawakami, M. Kanamori, Y. Morita, M. Miyama, and M. Yoshimoto, "A feed-forward dynamic voltage control algorithm for low power mpeg4 on multi-regulated voltage CPU," IEICE Trans. Electron., vol.E87-C, no.4, pp.3290-3297, April 2004.
3. T. Sakurai and A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol.25, no.2, pp.584-594, April 1990.
4. Joint Video Team (JVT) of ISO/IEC MPEG&ITU-T VCEG, ISO/IEC 14496-10, May 2003.
5. H. Iwasaki, J. Naganuma, Y. Nakajima, Y. Tashiro, K. Nakamura, T. Yoshitome, T. Onishi, M. Ikeda, T. Izuoka, and M. Endo, "A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumeroriented mobile codec systems," Proc. IEEE Custom Integrated Circuits Conference, pp.177-180, Sept. 2003.
6. S. Saponara, C. Blanch, K. Denolf, and J. Bormans, "The JVT advanced video coding standard: Complexity and performance analysis on a tool by tool basis," IEEE Packet Video 2003.
7. J. Chen, C. Chang, and Y. Lin, "A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC," IEEE International Symposium on Circuits and Systems, vol.5, pp.4525-4528, May 2005.
8. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A Vthvariation-tolerant SRAM with 0.3-V minimum operation voltage for memory-rich SoC under DVS environment," Digest of Technical Papers of 2006 Symposium on VLSI Circuits, pp.16-17, June 2006.
9. H.264/AVC reference software, http://iphome.hhi.de/suehring/tml/
10. http://www.celoxica.com/
11. H. Kawaguchi, Y. Shin, and T. Sakurai, "μITRON-LP: Power-conscious real-time OS based on cooperative voltage scaling for multimedia applications," IEEE Trans. Multimed., vol.7, no.1, pp.67-74, Feb. 2005.
12. K. Kawakami, M. Kanamori, Y. Morita, J. Takemura, M. Miyama, and M. Yoshimoto, "Power-minimum frequency/voltage cooperative management method for VLSI processor in leakage-dominant technology era," IEICE Trans. Fundamentals, vol.E88-A, no. 12, pp.3290-3297, Dec. 2005.