Connection test of area bump using active-matrix switches

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 4 B, 2005, Pages 2770-2773

  Watanabe, Naoya ^a   Hasegawa, Satoshi ^a   Asano, Tanemasa ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Active matrix; Bump connection test; System in package; Three dimensional integration

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; LSI CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; QUALITY CONTROL; SWITCHES;

ACTIVE MATRIX; BUMP CONNECTION TESTS; SYSTEM IN PACKAGE; THREE DIMENSIONAL INTEGRATION;

MOS DEVICES;

EID: 21244504984     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.44.2770     Document Type: Conference Paper

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