Examination of board-level drop reliability of package-on-package stacking assemblies of different structural configurations

Microelectronic Engineering

Volumn 84, Issue 1, 2007, Pages 87-94

  Lai, Yi Shao ^a   Yeh, Chang Lin ^a   Wang, Ching Chun ^a  

^a ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

JEDEC; Package on package (PoP); Pulse controlled drop test; Reliability

Indexed keywords

MICROELECTRONICS; NUMERICAL METHODS; RELIABILITY; STACKING FAULTS; STRUCTURAL DESIGN;

BOARD-LEVEL DROP RELIABILITY; PACKAGE-ON-PACKAGE STACKING ASSEMBLIES; PULSE-CONTROLLED DROP TEST CONDITION; STRUCTURAL CONFIGURATIONS; TIME INTEGRATION SOLVER;

ELECTRONICS PACKAGING;

EID: 33751525392     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2006.08.009     Document Type: Article

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