Prediction of board-level reliability of chip-scale packages under consecutive drops

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 1, Issue , 2005, Pages 73-80

  Yeh, Chang Lin ^a   Lai, Yi Shao ^a   Kao, Chin Li ^a  

^a ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION THEORY; IMPACT TESTING; INTEGRATED CIRCUIT MANUFACTURE; INVERSE KINEMATICS; SIGNAL FILTERING AND PREDICTION; SOLDERED JOINTS; STRAIN MEASUREMENT;

DROP IMPACTS; PLASTIC STRAIN ENERGIES; TRANSIENT STRUCTURAL RESPONSES;

CHIP SCALE PACKAGES;

EID: 33845569481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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