Gate current in stacked dielectrics for advanced FLASH EEPROM cells

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 317-320

  Driussi, F ^a   Marcuzzi, S ^a   Palestri, P ^a   Selmi, L ^a  

^a UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC PROPERTIES; ELECTRON MOBILITY; FLASH MEMORY; INSULATING MATERIALS; SILICA;

CHANNEL HOT ELECTRON (CHE); FOWLER-NORDHEIM (FN); NON VOLATILE MEMORY (NVM);

ELECTRIC CURRENTS;

EID: 33751426883     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546649     Document Type: Conference Paper

References (8)

1. P.Cappelletti et al. "Flash memory reliability", FLASH MEMORIES, Kluwer, p. 399, 1999.
2. K.Yoshikawa et al., "A Flash EEPROM cell Scaling Including Tunnel Oxide Limitations," Proc. ESS-DERC Conference, pp. P/2, 1990.
3. K.K.Likharev "Layered tunnel barriers for nonvolatile memory devices," Journal of Applied Physics, vol. 73, n. 15, pp. 2137-2139, 1998.
4. B.Govoreanu et al., "VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Mmeory Devices," IEEE EDL, vol. 24, n. 2, pp. 99-101, 2003.
5. J.Buckley et al., "Engineering of "Conduction Band Crested Barriers" or "Dielectric Constant Crested Barriers" in view of their application to Floating Gate Non Volatile Memory Devices," Silicon NanoElectronics Workshop, 2004.
6. A.Dalla Serra et al., "Closed and Open Boundary Models for Gate Current Calculations in MOS Devices," IEEE TED, vol. 48, n. 8, pp. 1811, 2001.
7. P.Palestri et al., "A Comparative Analysis of Substrate Current Generation Mechanisms in Tunneling MOS Capacitors," IEEE TED, vol. 49, n. 8, pp. 1427, 2002.
8. B.Govoreanu et al., "An investigation of the Electron Tunneling Leakage Current through Ultrathin Oxides/High-k gate Stacks at Inversion Conditions," Proc. SISPAD, pp. 287-290, 2003.