CMOS integration of solid phase epitaxy for sub-50nm devices

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 419-422

  Pouydebasque, A ^a   Dumont, B ^b   El Farhane, R ^a   Halimaoui, A ^b   Laviron, C ^c   Lenoble, D ^b   Rossato, C ^b   Casanova, N ^b   Carron, V ^c   Pokrant, S ^a   Skotnicki, T ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

^c CEA GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; EPITAXIAL GROWTH; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS;

CONTACT RESISTANCE; GATE CAPACITANCE; POLY-DEPLETION DEGRADATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33751423816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546674     Document Type: Conference Paper

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