A gate-level method for transistor-level bridging fault diagnosis

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 266-271

  Fan, Xinyue ^a   Moore, Will ^a   Hora, Camelia ^b   Konijnenburg, Mario ^b   Gronthoud, Guido ^b  

^a UNIVERSITY OF OXFORD   (United Kingdom)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGING FAULT DIAGNOSIS; TRANSISTOR LEVEL SIMULATION TOOLS;

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; FAULT TREE ANALYSIS;

GATES (TRANSISTOR);

EID: 33751119944     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.6     Document Type: Conference Paper

References (13)

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