A reconfigurable architecture for load-balanced rendering

Proceedings of the SIGGRAPH/Eurographics Workshop on Graphics Hardware

Volumn 2005, Issue , 2005, Pages 71-80

  Chen, Jiawen ^a   Gordon, Michael I ^a   Thies, William ^a   Zwicker, Matthias ^a   Pulli, Kari ^a,b   Durand, Frédo ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; PROBLEM SOLVING; RESOURCE ALLOCATION;

COMMODITY GRAPHICS HARDWARE; GRAPHICS PIPELINE; MULTICORE PROCESSORS; WORKLOADS;

COMPUTER GRAPHICS;

EID: 33750911771     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1071866.1071878     Document Type: Conference Paper

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